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[ABET Course Objectives and Outcomes Form] 
Course number and title:  EEM16 Logic Design of Digital Systems  
Credits:  4  
Instructor(s)incharge:  D. Cabric  (danijela@ee.ucla.edu)  
Course type:  Lecture  
Required or Elective:  Required.  
Course Schedule: 


Course Assessment: 


Grading Policy:  Typically 20% homework, 10% quizzes, 30% midterm, 40% final.  
Course Prerequisites:  
Catalog Description:  Introduction to digital systems. Specification and implementation of combinational and sequential systems. Standard logic modules and programmable logic arrays. Specification and implementation of algorithmic systems: data and controls sections. Number systems and arithmetic algorithms. Error control codes for digital information.  
Textbook and any related course material: 


Course Website  
Topics covered in the course and level of coverage: 


Course objectives and their relation to the Program Educational Objectives:  
Contribution of the course to the Professional Component: 


Expected level of proficiency from students entering the course: 


Material available to students and department at end of course:  


Will this course involve computer assignments? NO  Will this course have TA(s) when it is offered? YES 
Level of contribution of course to Program Outcomes  


:: Upon completion of this course, students will have had an opportunity to learn about the following :: 
Specific Course Outcomes  Program Outcomes  
1.  To convert numbers from/to Decimal to/from Binary and other Radix systems.  a  
2.  To derive equivalent switching expressions by applying transformations allowed in Boolean Algebra.  a  
3.  To determine the sum of minterms and product of maxterms that are equivalent to a given expression.  a  
4.  To analyze a given gate network and obtain a reduced switching expression for its outputs and to give its truth table.  a b i  
5.  To obtain a minimal sum of products of a given switching function by using Kmaps.  a c  
6.  To determine the state diagram and the minimized state table for a given sequential system.  a c  
7.  To determine the minimum delay of a given combinational network.  a b  
8.  To design sequential networks using SR flipflops, and/or T flipflops, and/or JK flipflops and/or D flipflops.  a c m  
9.  To design sequential (bitserial) adder/subtractor networks.  a c  
10.  To design a network of standard combinational modules with decoders, encoders, and shifters.  a c m  
11.  To design arithmetic combinational modules and networks using full adders and multipliers.  a c m  
12.  To represent signed integers in various ways including in twocomplement format.  a b  
13.  To design multimodule networks using registers, shift registers, and counter modules.  a c m  
14.  Several homework assignments reinforcing core concepts and skills learned in class.  a i  
15.  Opportunities to interact weekly with the instructor and the teaching assistant(s) during office hours and discussion sections in order to further their learning experience and their interest in the material.  i 
Program outcomes and how they are covered by the specific course outcomes  
(a)  ¤  To convert numbers from/to Decimal to/from Binary and other Radix systems.  
¤  To derive equivalent switching expressions by applying transformations allowed in Boolean Algebra.  
¤  To determine the sum of minterms and product of maxterms that are equivalent to a given expression.  
¤  To analyze a given gate network and obtain a reduced switching expression for its outputs and to give its truth table.  
¤  To obtain a minimal sum of products of a given switching function by using Kmaps.  
¤  To determine the state diagram and the minimized state table for a given sequential system.  
¤  To determine the minimum delay of a given combinational network.  
¤  To design sequential networks using SR flipflops, and/or T flipflops, and/or JK flipflops and/or D flipflops.  
¤  To design sequential (bitserial) adder/subtractor networks.  
¤  To design a network of standard combinational modules with decoders, encoders, and shifters.  
¤  To design arithmetic combinational modules and networks using full adders and multipliers.  
¤  To represent signed integers in various ways including in twocomplement format.  
¤  To design multimodule networks using registers, shift registers, and counter modules.  
¤  Several homework assignments reinforcing core concepts and skills learned in class.  
(b)  ¤  To analyze a given gate network and obtain a reduced switching expression for its outputs and to give its truth table.  
¤  To determine the minimum delay of a given combinational network.  
¤  To represent signed integers in various ways including in twocomplement format.  
(c)  ¤  To obtain a minimal sum of products of a given switching function by using Kmaps.  
¤  To determine the state diagram and the minimized state table for a given sequential system.  
¤  To design sequential networks using SR flipflops, and/or T flipflops, and/or JK flipflops and/or D flipflops.  
¤  To design sequential (bitserial) adder/subtractor networks.  
¤  To design a network of standard combinational modules with decoders, encoders, and shifters.  
¤  To design arithmetic combinational modules and networks using full adders and multipliers.  
¤  To design multimodule networks using registers, shift registers, and counter modules.  
(i)  ¤  To analyze a given gate network and obtain a reduced switching expression for its outputs and to give its truth table.  
¤  Several homework assignments reinforcing core concepts and skills learned in class.  
¤  Opportunities to interact weekly with the instructor and the teaching assistant(s) during office hours and discussion sections in order to further their learning experience and their interest in the material.  
(m)  ¤  To design sequential networks using SR flipflops, and/or T flipflops, and/or JK flipflops and/or D flipflops.  
¤  To design a network of standard combinational modules with decoders, encoders, and shifters.  
¤  To design arithmetic combinational modules and networks using full adders and multipliers.  
¤  To design multimodule networks using registers, shift registers, and counter modules.  
:: Last modified: February 2013 by J. Lin :: 